Only one transceiver common block is available per quad in an FPGA. In Virtex-7, Kintex-7, and Zynq-7000 SoC designs the common block contains the quad PLL that is used to clock the CPRI core and GTXE2/GTHE2 transceiver at the 9,830.4, 10,137.6, and 12165.12 Mb/s line rates. This block is also instantiated in cores operating at below these rates to correctly set the BIAS_CFG parameter. In Artix-7 based designs, the common block contains the PLL that is used to clock the GTPE2 transceiver at all line rates. In UltraScale architecture designs the common block is only instantiated in cores supporting line rates of 10,137.6 Mb/s and over.
When more than one CPRI core is present in the quad region a single common block is instantiated in the core support layer of one of the CPRI instances. The outputs from the common block are routed to the quad PLL clock ports of the core layers as described in Table: Transceiver Interface Signals (Core Generated without Core Support Layer) and Table: Transceiver Interface Signals (Core Generated with Core Support Layer) .
It might be desirable to retain independent transmitter clocks for CPRI cores instantiated in the same quad and to share only the transceiver common block between them. In this case the CPRI cores should be generated without the core support layer. The support blocks provided in the example design can be used to provide the clocking and reset signals for each instance of the CPRI core. An example with two CPRI cores is shown in This Figure .
The unused ports of the <component_name>_tx_alignment block should be looped back so that txphalign_vec drives txphaligndone_vec , txdlysreset_vec drives txdlysresetdone_vec and txphinit_vec drives txphinitdone_vec .
