• 9,830 and 10,137.6 Mb/s are only supported on -2 and -3 speed grades for Virtex-7 devices. These designs are implemented using a 32-bit datapath.
• 12,165.12 Mb/s line rates are only supported on -3 speed grades in FFG packages for Virtex-7, Kintex-7, and Zynq-7000 SoC devices. These designs are implemented with a 32-bit datapath.
• 9,830 and 10,137.6 Mb/s are only supported on -2 and -3 speed grades in FFG packages for Kintex-7 and Zynq-7000 SoC devices. These designs are implemented using a 32-bit datapath.
• CPRI designs supporting maximum line rates of 6,144 Mb/s require the use of a 32-bit datapath in Virtex-7, Kintex-7, and Zynq-7000 SoC devices with a speed grade of -1 or -2L. See the Virtex-7 and Kintex-7 FPGA data sheets for more information
• Line rates up to 12,165.12 Mb/s are supported on UltraScale and UltraScale+ devices, with the exception of GTHE3 transceiver-based cores using -1 speed grade parts. In these parts the maximum line rate is 10,137.6 Mb/s.
• Line rates of up to 24,330.24 Mb/s are supported on -2 and -3 speed grade Virtex UltraScale devices using the GTYE3 transceiver and on -1, -2, and -3 speed grade UltraScale+ devices using the GTYE4 transceiver.
IMPORTANT: In this product guide where a feature is referred to with the phrase “cores supporting x Mb/s”, this also implies its sub-line rates. For example, “cores supporting 3,072 Mb/s” also implies 2,457.6, 1,228.8 and 614.4 Mb/s; “cores supporting 6,144 Mb/s” also implies 4,915.2 Mb/s; “cores supporting 12,165.12 Mb/s” also implies 8,110.08 Mb/s.