Core I/Q Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

The transmit delay for the I/Q interface is shown in This Figure . A data word is clocked into the CPRI core on the client-side interface, and below that the first encoded data bit from that word is sent on the output pin of the transceiver. T tx is the delay between those two events.

Figure 4-21: Transmit Delay, Raw I/Q Interface

X-Ref Target - Figure 4-21

delay_raw_tx.jpg

The overall delay T tx is made up of the contributions listed in Table: Contributions to Transmit Delay, GTYE3 Transceiver . Unless stated these delays are for a GTYE3 transceiver-based implementation.

For other transceiver-based implementations, the calculation is similar but uses the transceiver latencies for the relevant device.

Table 4-15: Contributions to Transmit Delay, GTYE3 Transceiver

Contribution

Delay

16-bit cores up to 3,072.0 Mb/s

16-bit cores up to 4,915.2/6,144.0 Mb/s

32-bit cores up to 9,830.4 Mb/s

32-bit cores up to 10,137.6 Mb/s

64-bit cores up to 24,330.24 Mb/s

FPGA logic

(T CORETX )

40 UI

80 UI

160 UI

132 UI

396 UI

TX gearbox delay (T TGB )

N/A

Read back TX gearbox latency from the management interface and convert to UI as described in performing the cable delay calculation.

GTYE3 transceiver

delay (T GTYTX )

99 UI

99 UI

189 UI

190 UI

352 UI

Total (T TX )

139 UI

179 UI

349 UI

322 UI + T GB

748 UI + T TGB

The receive delay for the raw I/Q interface is shown in This Figure . The figure shows the first encoded bit of a data word being received by the transceiver, and the corresponding data word being clocked out of the CPRI core on the raw I/Q receive interface. T rx is the delay between those events.

X-Ref Target - Figure 4-22

Figure 4-22: Receive Delay, Raw I/Q Interface
delay_raw_rx.jpg

Table: Contributions to Receive Delay GTYE3 Transceiver lists the contributions that comprise the overall delay T rx.

Table 4-16: Contributions to Receive Delay GTYE3 Transceiver

Contribution

Delay

16-bit cores up to 3,072.0 Mb/s

16-bit cores up to

4,915.2/6,144.0 Mb/s

32-bit cores up to 9,830.4 Mb/s

32-bit cores up to 10,137.6 Mb/s

64-bit cores up to 24,330.24 Mb/s

GTYE3 transceiver

delay (T GTYRX )

134.5 UI

134.5 UI

256.5 UI

129.5 UI

225.5 UI

Barrel shift

(T BARREL )

Read back barrel shift latency in UI from the management interface.

N/A

Rx gearbox delay (T RGB )

N/A

Read back Rx gearbox latency from the management interface and convert to UI as described in performing the cable delay calculation.

Rx CDC FIFO

transit time

(T FIFO )

Read back Rx CDC FIFO transit time from the management interface and convert to UI as described in Delay Across the CDC FIFO .

FPGA logic

(T CORERX )

60 UI

80 UI

160 UI

165 UI

396 UI

Total (T RX )

194.5 UI + T BARREL + T FIFO

214.5 UI + T BARREL + T FIFO

416.5 UI + T BARREL + T FIFO

294.5 UI + T RGB + T FIFO

621.5 UI + T RGB + T FIFO