Synthesizable Example Design - 5.2 English

Video Mixer LogiCORE IP Product Guide (PG243)

Document ID
PG243
Release Date
2024-01-02
Version
5.2 English

The difference between the Synthesizable design and the Simulation example design is the use of a microprocessor instead of the AXI VIP core as AXI4 master. In addition, the synthesizable design uses the MIG IP core for DDR memory access. The locked port of AXI4-Stream to Video Out is connected to axi_gpio_lock core and the processor polls the corresponding register for a sign that the test passed. This Figure shows a synthesizable example design.

Figure 5-2: Synthesizable Example Block Design

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v-mix-syn-des.png

The synthesizable example design requires both Vivado and AMD Vitis™ tools.

The first step is to run synthesis, implementation, and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware . In the window, select Include bitstream , select an export directory and click OK to create an XSA project.

Figure 5-3: Export Hardware

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Vitis_XSA_Creation.png

The remaining work is performed in the AMD Vitis tool. The Video Mixer example design file can be found in the following Vitis directory:

(<install_directory>/<release>/data/embeddedsw/XilinxProcessorIPLib/drivers/v_mix_v6_1/examples/

The example application design source files (contained within examples folder) are tightly coupled with the v_mix example design available in Vivado IP catalog.

Perform the following steps to get the .elf file from the Vitis application.

1. Open the Vitis application.

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2. Select the new application project in File > New Application Project .

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3. Select a platform to create the project.

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4. Select the required xsa.

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5. Click Next .

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6. Name the application.

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7. Select the processor and click Next .

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8. Select the empty application.

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9. Import the required files.

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10. Build the project.

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11. For the elf file, check the debug folder.

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The vmix_example.tcl automates the process of generating the downloadable bit and elf files from the provided example xsa file.

To run the provided Tcl script:

1. Copy the exported example design xsa file in the examples directory of the driver

2. Launch the Xilinx Software Command-Line Tool (xsct) terminal

3. cd into the examples directory

4. Source the tcl file xsct :

%>source vmix_example.tcl

5. Execute the script:

xsct%>vmix_example xsa_file_name.xsa

The Tcl script performs the following:

Create workspace

Create HW project

Create BSP

Create Application Project

Build BSP and Application Project

After the process is complete, the required files are available in:

bit file ->v_mix_0_ex/ folder

elf file -> v_mix_0_ex/sdk/xv_mix_example_1{Debug/Release} folder

Next, perform the following steps to run the software application:

IMPORTANT: To do so, make sure that the hardware is powered on and a Digilent Cable or an USB Platform Cable is connected to the host PC. Also, ensure that a USB cable is connected to the UART port of the board.

1. Launch the Vitis application.

2. Set workspace to vmix_example.sdk folder in prompted window. The SDK project opens automatically (if a welcome page shows up, close that page).

3. Download the bitstream into the FPGA by selecting Xilinx Tools > Program FPGA . The Program FPGA dialog box opens.

4. Ensure that the Bitstream field shows the bitstream file generated by Tcl script, and then click Program .

Note: The DONE LED on the board turns green if the programming is successful.

5. A terminal program (HyperTerminal or PuTTY) is needed for UART communication. Open the program, choose appropriate port, set baud rate to 115,200, and establish Serial port connection.

6. Select and right-click the application vmix_example_design in Project_Explorer panel.

7. Select Run As > Launch on Hardware (GDB) .

8. Select Binaries and Qualifier in window and click OK .

The example design test result are shown in terminal program.