AXI4-Lite Control Interface - 5.2 English

Video Mixer LogiCORE IP Product Guide (PG243)

Document ID
PG243
Release Date
2024-01-02
Version
5.2 English

The AXI4-Lite interface allows you to dynamically control parameters within the core. The configuration can be accomplished using an AXI4-Lite master state machine, an embedded ARM ® , or soft system processor such as AMD MicroBlaze™. The Video Mixer can be controlled through the AXI4-Lite interface by using functions provided by the driver in the Vitis. Another method is performing read and write transactions to the register space but should only be used when the first method is not available. Table: AXI4-Lite Control Interface Signals shows the AXI4-Lite control interface signals. This interface runs at the ap_clk clock.

Table 2-9: AXI4-Lite Control Interface Signals

Signal Name

I/O

Width

Description

s_axi_ctrl_aresetn

I

1

Reset

s_axi_ctrl_aclk

I

1

Clock

s_axi_ctrl_awaddr

I

18

Write Address

s_axi_ctrl_awprot

I

3

Write Address Protection

s_axi_ctrl_awvalid

I

1

Write Address Valid

s_axi_ctrl_awready

O

1

Write Address Ready

s_axi_ctrl_wdata

I

32

Write Data

s_axi_ctrl_wstrb

I

4

Write Data Strobe

s_axi_ctrl_wvalid

I

1

Write Data Valid

s_axi_ctrl_wready

O

1

Write Data Ready

s_axi_ctrl_bresp

O

2

Write Response

s_axi_ctrl_bvalid

O

1

Write Response Valid

s_axi_ctrl_bready

I

1

Write Response Ready

s_axi_ctrl_araddr

I

18

Read Address

s_axi_ctrl_arprot

I

3

Read Address Protection

s_axi_ctrl_arvalid

I

1

Read Address Valid

s_axi_ctrl_aready

O

1

Read Address Ready

s_axi_ctrl_rdata

O

32

Read Data

s_axi_ctrl_rresp

O

2

Read Data Response

s_axi_ctrl_rvalid

O

1

Read Data Valid

s_axi_ctrl_rready

I

1

Read Data Ready