Memory Mapped AXI4 Interface - 5.2 English

Video Mixer LogiCORE IP Product Guide (PG243)

Document ID
PG243
Release Date
2024-01-02
Version
5.2 English

Per memory layer, there is a memory mapped AXI4 interface named m_axi_mm_video i with i representing the layer number minus 1. The memory mapped AXI4 interface runs on the ap_clk clock domain. The signals follow the specification as defined in the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 1] . Table: Pixel Formats shows the pixel formats in memory supported by the Video Mixer.

Table 2-8: Pixel Formats

Video Format

Description

Bits per Component

Bytes per Pixel

RGBX8

packed RGB

8

4 bytes per pixel

BGRX8

packed BGR

8

4 bytes per pixel

YUVX8

packed YUV 4:4:4

8

4 bytes per pixel

YUYV8

packed YUV 4:2:2

8

2 bytes per pixel

UYVY8

packed YUV 4:2:2

8

2 bytes per pixel

RGBA8

packed RGB with alpha

8

4 bytes per pixel

BGRA8

packed BGR with alpha

8

4 bytes per pixel

YUVA8

packed YUV 4:4:4

8

4 bytes per pixel

RGBX10

packed RGB

10

4 bytes per pixel

YUVX10

packed YUV 4:4:4

10

4 bytes per pixel

RGB565

packed RGB

5 bits per R component
6 bits per G component
5 bits per B component

2 bytes per pixel

BGR8

packed BGR

8

3 bytes per pixel

Y_UV8

semi-planar YUV 4:2:2

8

1 byte per pixel per plane

Y_UV8_420

semi-planar YUV 4:2:0

8

1 byte per pixel per plane

RGB8

packed RGB

8

3 bytes per pixel

YUV8

packed YUV 4:4:4

8

3 bytes per pixel

Y_UV10

semi-planar YUV 4:2:2

10

4 bytes per 3 pixels per plane

Y_UV10_420

semi-planar YUV 4:2:0

10

4 bytes per 3 pixels per plane

Y8

packed luma only

8

1 byte per pixel

Y10

packed luma only

10

4 bytes per 3 pixels

The following tables explain the expected pixel mappings in memory for each of the mentioned listed formats.