有关串联配置设计或 Dynamic Function eXchange 设计的特殊注意事项 - 1.3 简体中文

UltraScale+ 器件 Integrated Block for PCI Express 产品指南 (PG213)

Document ID
PG213
Release Date
2022-11-16
Version
1.3 简体中文

串联配置和 Dynamic Function eXchange (DFX) 设计可能具有额外的注意事项需要考量,因为这些流程会将物理资源分区到多个独立区域内。在将调试 IP 添加到设计中(例如,VIO、ILA、MDM 和 MIG-IP)时,应考量使用这些物理分区。专为From PCIe-ext to BSCANFrom AXI to BSCAN配置的 Debug Bridge IP 只能放置在设计的静态分区内。在 DFX 或串联现场更新区域内使用调试 IP 时,应将另一个调试 BSCAN 接口添加到动态区域模块定义中,并在动态区域模块例化过程中使其保持未连接状态。

要将 BSCAN 接口添加到可重配置分区定义中,应将相应的端口和端口属性添加到可重配置分区定义中。以下提供的 Verilog 可用作为将 BSCAN 接口添加到端口声明的模板。

...
// BSCAN interface definition and attributes.
// This interface should be added to the DFX module definition
// and left unconnected in the DFX module instantiation.
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN drck" *)
(* DEBUG="true" *)
input S_BSCAN_drck,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN shift" *)
(* DEBUG="true" *)
input S_BSCAN_shift,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tdi" *)
(* DEBUG="true" *)
input S_BSCAN_tdi,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN update" *)
(* DEBUG="true" *)
input S_BSCAN_update,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN sel" *)
(* DEBUG="true" *)
input S_BSCAN_sel,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tdo" *)
(* DEBUG="true" *)
output S_BSCAN_tdo,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tms" *)
(* DEBUG="true" *)
input S_BSCAN_tms,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tck" *)
(* DEBUG="true" *)
input S_BSCAN_tck,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN runtest" *)
(* DEBUG="true" *)
input S_BSCAN_runtest,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN reset" *)
(* DEBUG="true" *)
input S_BSCAN_reset,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN capture" *)
(* DEBUG="true" *)
input S_BSCAN_capture,
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN bscanid_en" *)
(* DEBUG="true" *)
input S_BSCAN_bscanid_en,
....

运行 link_design 时,公开的端口将通过工具自动化连接到调试网络的静态部分。ILA 也会根据设计需要连接到调试网络。在设计顶层可能还会添加另一个 dbg_hub 单元。对于含现场更新的串联 PCIe 设计,dbg_hub 和工具插入的时钟缓冲器必须添加到相应的设计分区。以下是完成 opt_design 后可运行的 Tcl 命令示例,这些命令用于将 dbg_hub 原语与相应的设计分区加以关联。

# Add the inserted dbg_hub cell to the appropriate design partition.
set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub]
# Add the clock buffer to the appropriate design partition.
set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells dma_pcie_0_support_i/
pcie_ext_cap_i/vsec_xvc_inst/vsec_xvc_dbg_bridge_inst/inst/bsip/ins
t/USE_SOFTBSCAN.U_TAP_TCKBUFG]