参考资料 - 5.0 简体中文

QDMA Subsystem for PCI Express 产品指南 (PG302)

Document ID
PG302
Release Date
2023-10-18
Version
5.0 简体中文

以下技术文档是非常实用的补充资料,可配合本产品指南一起使用:

  1. Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express 产品指南(PG344)
  2. AMBA AXI4‑Stream 协议规范(ARM IHI 0051A)
  3. PCI-SIG 规范(www.pcisig.com/specifications)
  4. Virtex 7 FPGA Integrated Block for PCI Express LogiCORE IP 产品指南(PG023)
  5. 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP 产品指南(PG054)
  6. UltraScale 器件 Gen3 Integrated Block for PCI Express LogiCORE IP 产品指南(PG156)
  7. AXI Bridge for PCI Express Gen3 Subsystem 产品指南(PG194)
  8. DMA/Bridge Subsystem for PCI Express 产品指南(PG195)
  9. UltraScale+ Integrated Block for PCI Express LogiCORE IP 产品指南(PG213)
  10. Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express 产品指南(PG344)
  11. Vivado Design Suite:AXI 参考指南(UG1037)
  12. Vivado Design Suite 用户指南:采用 IP integrator 设计 IP 子系统(UG994)
  13. Vivado Design Suite 用户指南:采用 IP 进行设计(UG896)
  14. Vivado Design Suite 用户指南:入门指南(UG910)
  15. Vivado Design Suite 用户指南:逻辑仿真(UG900)
  16. Vivado Design Suite 用户指南:使用约束(UG903)
  17. Vivado Design Suite 用户指南:烧录和调试(UG908)