VHDL 实数类型 - 2023.2 简体中文

Vivado Design Suite 用户指南: 逻辑仿真 (UG900)

Document ID
UG900
Release Date
2023-10-18
Version
2023.2 简体中文

单个 VHDL real 值在 C/C++ 中呈现为 double

代码示例:

// Put 3.14 on signal "myReal," where "myReal" is defined as
// signal myReal : real;
const double doubleVal = 3.14;
int myReal = loader.get_port_number("myReal");
loader.put_value(myReal, &doubleVal);