xelab - 2023.2 简体中文

Vivado Design Suite 用户指南: 逻辑仿真 (UG900)

Document ID
UG900
Release Date
2023-10-18
Version
2023.2 简体中文

用于给定顶层单元的 xelab 命令可执行下列操作:

  • 使用语言绑定规则或 -L <library> 命令行指定的 HDL 库加载子设计单元
  • 执行设计的静态细化(设置参数、泛型、使生成语言生效等)
  • 生成可执行代码
  • 将生成的可执行代码与仿真内核库相链接,以创建可执行仿真快照

随后,可使用产生的可执行仿真快照名称作为 xsim 命令的选项,搭配其他选项来影响 HDL 仿真。

提示: xelab 可隐式调用解析命令 xvlogxvhdl。您可使用 xelab -prj 选项整合解析步骤。如需了解有关工程文件的更多信息,请参阅 工程文件 (.prj) 语法
注释: xelabxvlogxvhdl 都不是 Tcl 命令。xvlogxvhdlxelab 均为 Vivado 无关的编译器可执行文件。因此,并没有对应的 Tcl 命令。

xelab 命令语法选项

在以下代码块中提供了每个选项的描述。

xelab 
[-d [define] <name>[=<val>]
[-debug <kind>]
[-f [-file] <filename>]
[-generic_top <value>]
[-h [-help]
[-i [include] <directory_name>]
[-initfile <init_filename>]
[-log <filename>]
[-L [-lib] <library_name> [=<library_dir>]
[-maxdesigndepth arg]
[-mindelay]
[-typdelay]
[-maxarraysize arg]
[-maxdelay]
[-mt arg]
[-nolog]
[-noname_unnamed_generate]
[-notimingchecks]
[-nosdfinterconnectdelays]
[-nospecify]
[-O arg]
[-override_timeunit]
[-override_timeprecision]
[-prj <filename>]
[-pulse_e arg]
[-pulse_r arg]
[-pulse_int_e arg]
[-pulse_int_r arg]
[-pulse_e_style arg]
[-r [-run]]
[-R [-runall]]
[-rangecheck]
[-relax]
[-s [-snapshot] arg]
[-sdfnowarn]
[-sdfnoerror]
[-sdfroot <root_path>]
[-sdfmin arg]
[-sdftyp arg]
[-sdfmax arg]
[-sourcelibdir <sourcelib_dirname>]
[-sourcelibext <file_extension>]
[-sourcelibfile <filename>]
[-stats]
[-timescale]
[-timeprecision_vhdl arg]
[-transport_int_delays]
[-v [verbose] [0|1|2]] 
[-version]
[-sv_root arg]
[-sv_lib arg]
[-sv_liblist arg]
[-dpiheader arg]
[-driver_display_limit arg]
[-dpi_absolute]
[-incr]
[-93_mode]
[-nosignalhandlers]
[-dpi_stacksize arg]
[-transform_timing_checkers]
[-a[ --standalone]
[-ignore_assertions]
[-ignore_coverage]
[-cov_db_dir arg]
[-cov_db_name arg]
[-uvm_version arg]
[-report_assertion_pass]
[-dup_entity_as_module]
[-cc_celldefines]
[-cc_libs]
[-cc_type arg]
[-cc_db arg]
[-cc_dir arg]
[-cov_db_dir arg]
[-cov_db_name arg]
[-ignore_localparam_override]
[-sc_lib arg]
[-sc_root arg]