下表列出了受支持的端口类型。
VHDL 1 | Verilog/SV 2 |
---|---|
IN | INPUT |
OUT | OUTPUT |
INOUT | INOUT |
|
下表显示了针对混用语言的设计边界上的端口受支持的 VHDL 和 Verilog 数据类型。
VHDL 端口 | Verilog 端口 |
---|---|
bit
|
信号线 |
std_logic
|
信号线 |
bit_vector
|
矢量信号线 |
signed
|
矢量信号线 |
unsigned
|
矢量信号线 |
std_ulogic_vector
|
矢量信号线 |
std_logic_vector
|
矢量信号线 |
注释: 在混用语言的边界上,支持类型为
reg
的 Verilog 输出端口。在边界上,reg
输出端口作为输出信号线(连线)端口来处理。混用语言边界上存在的任意其他类型的端口均视为错误。SV 数据类型 | VHDL 数据类型 |
---|---|
Int | |
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
byte |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
shortint |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
longint |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
integer |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
bit(1D) 的矢量 |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
logic(1D) 的矢量 |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
reg(1D) 的矢量 |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
logic/bit |
|
bit
|
|
std_logic
|
|
std_ulogic
|
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
注释: 支持用于例化具有真实端口的 Verilog 模块的 VHDL 实体。