Step 4: Using Vitis Analyzer - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

After emulation is complete, you can look at the profiling and VCD trace data that was also generated at the same time. Note that if profiling and VCD signal features are not used, emulation runs faster.

Using the XSIM Waveform GUI to view waveforms is powerful in allowing you to see the data path and flow of the design, as well as debug potential issues like a hang. However, this will only show the programmable logic side of the system. To investigate the AI Engine signals, you need to use the VCD trace in the Vitis analyzer. To use the Vitis analyzer, open up a .aierun_summary file.

  1. Open the run summary of the design by running the following command.

    vitis_analyzer sw/sim/behav_waveform/xsim/default.aierun_summary &
    

    When the summary is open, you should see something similar to the following.

    Vitis Analyzer Summary

  2. Here you can see various reports: Summary, Trace, Profile, Graph, Array. Click on Trace to open up the VCD data that was collected during hardware emulation.

    Vitis Analyzer Trace

    Here you can see the inner traces of the graph through a tile hierarchy. Selecting a net, tile, function, or any object in this view will cross-select to various views. This can help with identifying specific nets and functions.

  3. Open the Graph view and click on the Buffers tab.

  4. To find the RTP buffers, click on the search button (search) and type in coeffs.

    You should see a window like the following.

    rtp search

  5. Select the three coeffs buffers, and click the Trace view again, and see that the lock signals are highlighted.

    Selected RTP

  6. If you scroll up you can see that the FIR filter kernel begins to process data soon after the RTP is read.