Simulation - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

For comprehensive information about Vivado® simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).

You can simulate the example design using the open_example_project flow in Vivado® design tools.

If you open an example project, then the simulation scripts are generated in the working directory in:

example_project/<component_name>_example/<component_name>_example.sim/sim_1/

Simulation Waveforms for the Safe Clock Startup Feature without sequencing

Simulation, when Safe Clock Startup is true, is illustrated in the below snapshot.

Figure 1. Simulation, when Safe Clock Startup is true

The sequencing is disabled in the above configuration.

After LOCKED is high, clk_out1 will enable after 8 cycles to first clock out the frequency of primitive. Similarly, after LOCKED is high, clk_out2 will enable after 8 cycles to second clock out the frequency of primitive.

Similarly, after LOCKED is high, clk_out3 will enable after 8 cycles to third clock out frequency of primitive.

Similarly, after LOCKED is high, clk_out4 will enable after 8 cycles to fourth clock out frequency of primitive.

Simulation Waveforms for the Safe Clock Startup Feature with sequencing

The below figure illustrates simulation when Safe Clock Startup is true and Use Clock Sequencing is true, with the required sequence number in the table (Consider sequence is 1,2,3,4).

Figure 2. Simulation, when Safe Clock Startup is true and Use Clock Sequencing

After LOCKED is high, clk_out1 will enable after 8 cycles to the first clock out the frequency of primitive. And after CLKOUT1 is high, clk_out2 will enable after 8 cycles to the second clock out the frequency of primitive.

After CLKOUT2 is high, clk_out3 will enable after 8 cycles to the third clock out frequency of primitive.

After CLKOUT3 is high, clk_out4 will enable after 8 cycles to the fourth clock out frequency of primitive.

This will be useful if the user uses a case where the clocks need to come in sequence.